From: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx> Add PCIe support on the Verdin iMX8M Plus. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx> --- This has successfully been tested with Lucas' imx8mp-hsio-blk-ctrl high performance PLL clock exposure patch set [1] a later version thereof hopefully may land together with my humble patch. Thanks! [1] https://lore.kernel.org/all/20221213160112.1900410-1-l.stach@xxxxxxxxxxxxxx/ .../dts/freescale/imx8mp-verdin-dahlia.dtsi | 9 +++++++- .../boot/dts/freescale/imx8mp-verdin.dtsi | 22 ++++++++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 80db1ad7c230..56b0e4b865c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -67,7 +67,14 @@ &i2c4 { /* TODO: Audio Codec */ }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; /* Verdin PWM_1 */ &pwm1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 6a1890a4b5d8..f3a46f4caf49 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -749,7 +749,27 @@ eeprom_carrier_board: eeprom@57 { }; }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <10000000>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; +}; /* Verdin PWM_1 */ &pwm1 { -- 2.36.1
