Il 01/12/22 08:33, Allen-KH Cheng ha scritto:
Add adsp power domain controller node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
---
Ref: https://lore.kernel.org/all/2ec80bd8-dfef-d2e6-eb41-6e6088043e33@xxxxxxxxxxxxx/
[Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>]
---
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 ++++++++
include/dt-bindings/power/mt8192-power.h | 1 +
2 files changed, 9 insertions(+)
Allen, thanks for this one, but it's incomplete...
First of all, you must add the power domain on the driver itself, specifically,
in drivers/soc/mediatek/mt8192-pm-domains.h - otherwise this change will have no
effect!
...Then, as Chen-Yu said, you should also add the power domain to the scp_adsp
clock node as that's solving the lockup issue...
.......and last, but not least: we need a Fixes tag to backport this fix, here
and on the commit that adds the missing power domain in the driver.
Thanks,
Angelo
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 424fc89cc6f7..e71afba871fc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -514,6 +514,14 @@
};
};
};
+
+ power-domain@MT8192_POWER_DOMAIN_ADSP {
+ reg = <MT8192_POWER_DOMAIN_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP_SEL>;
+ clock-names = "adsp";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
};
};
diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h
index 4eaa53d7270a..63e81cd0d06d 100644
--- a/include/dt-bindings/power/mt8192-power.h
+++ b/include/dt-bindings/power/mt8192-power.h
@@ -28,5 +28,6 @@
#define MT8192_POWER_DOMAIN_CAM_RAWA 18
#define MT8192_POWER_DOMAIN_CAM_RAWB 19
#define MT8192_POWER_DOMAIN_CAM_RAWC 20
+#define MT8192_POWER_DOMAIN_ADSP 21
#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */
