Hi, On 30/11/2022 21:18, Geert Uytterhoeven wrote:
Hi Tomi, On Wed, Nov 23, 2022 at 8:00 AM Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx> wrote:Add clocks related to display which are needed to get the DSI output working. Extracted from Renesas BSP tree. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx> Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>Thanks for your patch!--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), + DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), @@ -161,6 +163,14 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), +Weird horizontal and vertical spacing below...
Yep. I added those to keep the lines more visible for me while working on this, but forgot to remove.
+ DEF_MOD("dis0", 411, R8A779G0_CLK_S0D3),I doubt this parent clock is correct. Based on Table 8.1.4e ("Lists of CPG clocks generated from PLL5"), this should be one of the VIOBUS clocks. VIOBUSD2 has the same rate as S0D3, so I'd use that one.
I'm pretty clueless about Renesas clocks, and I can't find a nice clock-tree picture from the docs, but looking at the table, what you say makes sense.
Both VIOBUS and VIOBUSD2 are marked to go to the video IPs, but with a bit of browsing, I can't find any more info about the clocking. Afaik, we don't care about the dis0 rate in the driver, so... Basically any clock will work here =). I'll pick VIOBUSD2 as you suggest (why would there be a /2 clock if it's not used...).
+ DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_DSIREF), + DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_DSIREF), + + DEF_MOD("fcpvd0", 508, R8A779G0_CLK_S0D3), + DEF_MOD("fcpvd1", 509, R8A779G0_CLK_S0D3),Likewise.
Ack.
+ DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1), @@ -193,6 +203,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4), + + DEF_MOD("vspd0", 830, R8A779G0_CLK_S0D1_VIO), + DEF_MOD("vspd1", 831, R8A779G0_CLK_S0D1_VIO),While S0D1_VIO is a VIO clock, it is clocked from PLL1, which supports spread-spectrum, unlike PLL5. Again, based on Table 8.1.4e ("Lists of CPG clocks generated from PLL5"), this should be one of the VIOBUS clocks.
Yep.
No, of the clocks added above, in the drivers we only care about the dsiref rate. That's used for the DSI PLL, and that PLL is used as the DU's pclk.Not that all of this matters a lot: all of these parents are always-on, and I think "dis0" is the only clock where we care about the actual clock rate?
Tomi
