Hi, On Mon, 28 Nov 2022 at 13:39, Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > On 22/11/2022 14:30, Dmitry Baryshkov wrote: > > Hi, > > > > On Mon, 21 Nov 2022 at 19:07, Krzysztof Kozlowski > > <krzysztof.kozlowski@xxxxxxxxxx> wrote: > >> > >> On 21/11/2022 11:36, Yassine Oudjana wrote: > >>> > >>> On Mon, Nov 21 2022 at 09:26:59 +01:00:00, Krzysztof Kozlowski > >>> <krzysztof.kozlowski@xxxxxxxxxx> wrote: > >>>> On 20/11/2022 16:46, Yassine Oudjana wrote: > >>>>>>> + interrupts: > >>>>>>> + items: > >>>>>>> + - description: Charger error > >>>>>>> + - description: Charger inhibited > >>>>>>> + - description: Charger precharge safety timer timeout > >>>>>>> + - description: Charger charge safety timer timeout > >>>>>>> + - description: Charger pre to fast charging switch > >>>>>>> threshold reached > >>>>>>> + - description: Charger recharge threshold reached > >>>>>>> + - description: Charger taper threshold reached > >>>>>>> + - description: Charger charge termination threshold reached > >>>>>>> + - description: Battery hot > >>>>>>> + - description: Battery warm > >>>>>>> + - description: Battery cold > >>>>>>> + - description: Battery cool > >>>>>>> + - description: Battery overvoltage > >>>>>>> + - description: Battery low > >>>>>>> + - description: Battery missing > >>>>>>> + - description: Battery thermistor missing # unconfirmed > >>>>>>> + - description: USB input undervolt > >>>>>>> + - description: USB input overvolt > >>>>>>> + - description: USB input source detected > >>>>>>> + - description: OTG regulator failure > >>>>>>> + - description: OTG regulator overcurrent > >>>>>>> + - description: Automatic input current limiting done > >>>>>>> + - description: USB ID pin changed > >>>>>>> + - description: DC input undervolt > >>>>>>> + - description: DC input overvolt > >>>>>>> + - description: Power OK > >>>>>>> + - description: Temperature shutdown > >>>>>>> + - description: Watchdog timeout > >>>>>>> + - description: Flash failure > >>>>>>> + - description: OTST2 # unknown > >>>>>>> + - description: OTST3 # unknown > >>>>>> > >>>>>> It seems you listed register interrupts, not physical pins. This > >>>>>> should > >>>>>> be interrupt lines. > >>>>> > >>>>> I'm not sure what I'm supposed to do here. I couldn't find an > >>>>> interrupt-lines > >>>>> property used anywhere so that's not what you meant, right? > >>>> > >>>> Are these physical interrupt lines this device has, register offsets > >>>> or > >>>> virtual interrupts (e.g. passed via irq_chip)? Definitely not the > >>>> first > >>>> and rather offsets for qpnpint_irq_domain_translate. Devicetree is not > >>>> for describing register layout of devices. IOW, register layout does > >>>> not > >>>> change on different boards, because the device is exactly the same, so > >>>> there is no point to put it into DTS. > >>>> > >>> > >>> So how would I describe the interrupts then? Or if you are saying I > >>> shouldn't have these interrupts in DT at all, how would I get them and > >>> register handlers for them in the driver? the PMIC arbiter takes 4 > >>> interrupt cells, 3 of which are these offsets specifying the peripheral > >>> and interrupt. All other PMIC peripherals currently described in DT > >>> (examples being qcom,pm8916-wcd-analog-codec, qcom,pm8941-pwrkey and > >>> qcom-wled) have their interrupts (if any) described this way, with the > >>> only exceptions perhaps being the GPIO and MPP controllers which are > >>> themselves interrupt controllers. Changing the way PMIC peripheral > >>> interrupts are described would require changing PMIC arbiter bindings > >>> and code which I believe is out of the scope of this patch series. > >> > >> I don't think this would touch PMIC arbiter bindings, rather the PMIC > >> itself. Usually complex devices (like PMICs) have one few physical > >> interrupt lines and many registers related to some specific interrupts. > >> For example: > >> 1. One IRQ line, > >> 2. Register with bits for overvoltage, undervoltage, vharger error etc. > >> > >> Now how the MFD child device accesses them. Since this is strictly > >> related to hardware programming model, it's not something you put to > >> Devicetree. Instead parent device (PMIC) registers IRQ chip for its one > >> interrupt line with several Linux (or virtual) interrupts. The children > >> then just get a virtual IRQ from the parent (PMIC) and setup a > >> handler(s) for them. > > > > Unfortunately this is not how SPMI PMICs work (at least on the > > Qualcomm platforms). Access to interrupt registers is handled via the > > SPMI bus arbiter writes, not through the GPIO pin or typical spmi's > > bus interface (in the other words, not through the PMIC's SPMI > > regmap). > > I am not sure how this is related... Just because they do not use same > regmap/interface does not mean that child device should have register > bits as interrupt sources. Do you model I2C PMICs devices the same way? > No. They get the interrupts from the parent and how the parent handles > them (same or different regmap) is separate problem. For i2c PMICs it's typically not the case, since the interrupt is OOB. It is an external GPIO pin, as you have described previously. For Qcom SPMI PMIC the interrupts are really handled by the SPMI host controller (arbieter). So the DT really represents the hardware. > > The charger node does not make SPMI bus as interrupt parent, so these > interrupts are going to the SPMI PMIC don't they? or is it mistake in > DTS - lack of interrupt-parent? I thought that with the lack of the interrupt-parent, the OS will traverse the tree up until it finds one. Is it so? > > I guess we can add an intermediate irq chip to automatically > > handle the USID, etc. However I doubt that it will really bring a lot > > in our case. > > The charger node defines all interrupts with SID=2, which is also not > really correct. The parent device is SID=2. The child - does not matter. > DT is a tree for some reason... Yes, I agree with you. The bindings do not look ideal here. I was trying to point out that this is not a problem with the smbchg device only. Other Qcom SPMI PMIC devices also use exactly the same approach (except gpio and mpps). So, we can either: - Continue using the current approach - Rework pmic driver to provide an intermediate IRQ domain. This would require finding a way to ping SPMI ARB's IRQ registers from PMIC controller (via callbacks, via extra interrupt translation, etc). -- With best wishes Dmitry
