On 23/11/2022 07.06, Rob Herring wrote: > The t600x CPU nodes are missing the cache hierarchy information. The > cache hierarchy on Arm can not be detected and needs to be described in > DT. The OS scheduler can make use of this information for scheduling > decisions. > > The cache size information is based on various articles about the > processors. There's also an L3 system level cache (SLC). It's not > described here because SLCs typically have some MMIO interface which > would need to be described. > > Signed-off-by: Rob Herring <robh@xxxxxxxxxx> > --- > Based on apple dts changes in linux-next. > > This fixes the warning: Unable to detect cache hierarchy for CPU %d > --- > arch/arm64/boot/dts/apple/t6002.dtsi | 51 +++++++++++++++++++++ > arch/arm64/boot/dts/apple/t600x-common.dtsi | 51 +++++++++++++++++++++ > 2 files changed, 102 insertions(+) > [...] Applied to asahi-soc/dt, thanks! I probably won't send this one up until the 6.3 cycle; I've rebased our downstream bits/000-devicetree on top so it'll get some downstream testing before going upstream (and in the meantime someone should get around to adding these for the other chips too ;)). Cheers, - Hector
