On Fri, 18 Nov 2022 at 13:01, Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Fri, Nov 18, 2022 at 09:17:12AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@xxxxxxxx>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx>
> > Co-developed-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
> > Co-developed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
> > 1 file changed, 437 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..c22e8f1d2640
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -0,0 +1,437 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@xxxxxxxx>
>
> @Emil, I feel like I have to ask given the 2022 date, but should this
> stuff be attributed to your canonical address or is this fine?
Yeah, this is fine. I did this on my own time before I was actually
tasked with working on the JH7110 based boards.
> Other than that, a cursory check /looks/ fine, other than the:
>
> > + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
> > + };
>
> If you remove the clock-frequency = <0> bit, dtb validation will force
> people to set the value in jh7110-board.dts which I'd prefer to rely on
> than a comment.
>
> Glad to see you sorted out the clock/reset stuff too!
>
> Thanks,
> Conor.
>
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