On 9/30/22 23:39, Rob Herring wrote:
On Fri, Sep 30, 2022 at 03:00:28PM +0200, Michal Simek wrote:
Hi Rob,
On 9/30/22 14:25, Rob Herring wrote:
On Fri, Sep 30, 2022 at 3:04 AM Shubhrajyoti Datta
<shubhrajyoti.datta@xxxxxxx> wrote:
The Clocking Wizard for Versal adaptive compute acceleration platforms
generates multiple configurable number of clock outputs.
Add device tree binding for Versal clocking wizard support.
Really v1? I'm sure I heard of this wizard before.
What about this?:
drivers/staging/clocking-wizard/dt-binding.txt
That needs to be moved out of staging rather than adding a 2nd one.
Let me clarify this. This is IP which is already moved out of staging.
Linux-next has these changes and waiting for MW to happen (already in clock
tree).
Where does this series explain that? If the dependency is not the latest
rc1, then state that.
Please take a look below.
And this is new IP. Not sure who has chosen similar name but this targets
Xilinx Versal SOCs. Origin one was targeting previous families.
Do we need a whole new schema doc?
It is completely new IP with different logic compare to origin one.
It is not ideal to define the same property, xlnx,nr-outputs, more than
once. And it's only a new compatible string.
I can't see any issue with using dt binding for xlnx,clocking-wizard.yaml
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
also for this IP if that's fine with you.
Only xlnx,speed-grade can be defined for previous IP which is easy to mark.
But as I said, driver is different and integrating to current driver is not a
good idea. But if two separate drivers can use the same DT binding document with
adding new compatible string (and small tweak around one dt property) then it
shouldn't be a problem to do it in v2.
Thanks,
Michal
