On Fri, Sep 30, 2022 at 3:04 AM Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> wrote: > > The Clocking Wizard for Versal adaptive compute acceleration platforms > generates multiple configurable number of clock outputs. > Add device tree binding for Versal clocking wizard support. Really v1? I'm sure I heard of this wizard before. What about this?: drivers/staging/clocking-wizard/dt-binding.txt That needs to be moved out of staging rather than adding a 2nd one. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> > --- > > .../bindings/clock/xlnx,clk-wizard.yaml | 66 +++++++++++++++++++ > 1 file changed, 66 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml > new file mode 100644 > index 000000000000..41a6f4bcaccd > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/xlnx,clk-wizard.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Versal clocking wizard > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> > + > +description: > + The clocking wizard is a soft ip clocking block of Xilinx versal. The IP > + uses the input clock frequencies and generates the requested > + clock output. > + > +properties: > + compatible: > + const: xlnx,clk-wizard-1.0 Where does 1.0 come from? A 1.0 always feels made up. This should be based on some IP versioning that's documented somewhere. > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + clocks: > + description: List of clock specifiers which are external input > + clocks to the given clock controller. > + items: > + - description: functional clock input > + - description: axi clock or the interface clock > + > + clock-names: > + items: > + - const: clk_in1 > + - const: s_axi_aclk > + > + xlnx,nr-outputs: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 8 > + description: > + Number of outputs. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - clocks > + - clock-names > + - xlnx,nr-outputs > + > +additionalProperties: false > + > +examples: > + - | > + clock-generator@40040000 { > + compatible = "xlnx,clk-wizard-1.0"; > + reg = <0x40040000 0x1000>; > + #clock-cells = <1>; > + clocks = <&clkc 15>, <&clkc 15>; > + clock-names = "clk_in1", "s_axi_aclk"; > + xlnx,nr-outputs = <6>; > + }; > +... > -- > 2.17.1 >
