On 18/09/2022 20:28, Tomer Maimon wrote:
> Hi Rob,
>
> Thanks for your comment and sorry for the late reply.
Two months... we are out of the context and this will not help your
patchset.
>
> On Tue, 19 Jul 2022 at 00:10, Rob Herring <robh@xxxxxxxxxx> wrote:
>>
(...)
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> + #include <dt-bindings/gpio/gpio.h>
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + pinctrl: pinctrl@f0800000 {
>>> + compatible = "nuvoton,npcm845-pinctrl";
>>> + ranges = <0x0 0x0 0xf0010000 0x8000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + nuvoton,sysgcr = <&gcr>;
>>> +
>>> + gpio0: gpio@f0010000 {
>>
>> gpio@0
>>
>> Is this really a child block of the pinctrl? Doesn't really look like it
>> based on addressess. Where are the pinctrl registers? In the sysgcr? If
>> so, then pinctrl should be a child of it. But that doesn't really work
>> too well with gpio child nodes...
> the pin controller mux is handled by sysgcr this is why the sysgcr in
> the mother node,
> and the pin configuration are handled by the GPIO registers. each
> GPIO bank (child) contains 32 GPIO.
> this is why the GPIO is the child node.
Then maybe pinctrl should be the sysgcr and expose regmap for other devices?
Best regards,
Krzysztof
