> + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + phy-handle = <ða0>; > + phy-mode = "sgmii"; > + #address-cells = <1>; > + #size-cells = <0>; > + etha0: ethernet-phy@0 { > + reg = <1>; reg = 1 means you should have @1. > + compatible = "ethernet-phy-ieee802.3-c45"; > + }; > + }; You are mixing Ethernet and MDIO properties in one node. Past experience says this is a bad idea, particularly when you have switches involved. I would suggest you add an mdio container: > + port@1 { > + reg = <1>; > + phy-handle = <ða1>; > + phy-mode = "sgmii"; > + #address-cells = <1>; > + #size-cells = <0>; mdio { > + etha1: ethernet-phy@1 { > + reg = <2>; > + compatible = "ethernet-phy-ieee802.3-c45"; > + }; }; > + }; > + port@2 { > + reg = <2>; > + phy-handle = <ða2>; > + phy-mode = "sgmii"; > + #address-cells = <1>; > + #size-cells = <0>; > + etha2: ethernet-phy@2 { > + reg = <3>; > + compatible = "ethernet-phy-ieee802.3-c45"; > + }; > + }; I find it interesting you have PHYs are address 1, 2, 3, even though they are on individual busses. Why pay for the extra pullup/down resistors when they could all have the same address? Andrew