On Mon 15 Aug 2022 at 21:20, Yu Tu <yu.tu@xxxxxxxxxxx> wrote:
>>>> +
>>>> +static struct clk_regmap s4_hdmi_pll_dco = {
>>>> + .data = &(struct meson_clk_pll_data){
>>>> + .en = {
>>>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>> + .shift = 28,
>>>> + .width = 1,
>>>> + },
>>>> + .m = {
>>>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>> + .shift = 0,
>>>> + .width = 8,
>>>> + },
>>>> + .n = {
>>>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>> + .shift = 10,
>>>> + .width = 5,
>>>> + },
>>>> + .frac = {
>>>> + .reg_off = ANACTRL_HDMIPLL_CTRL1,
>>>> + .shift = 0,
>>>> + .width = 17,
>>>> + },
>>>> + .l = {
>>>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>> + .shift = 31,
>>>> + .width = 1,
>>>> + },
>>>> + .rst = {
>>>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>> + .shift = 29,
>>>> + .width = 1,
>>>> + },
>>>> + },
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "hdmi_pll_dco",
>>>> + .ops = &meson_clk_pll_ro_ops,
>>>> + .parent_data = (const struct clk_parent_data []) {
>>>> + { .fw_name = "xtal", }
>>>> + },
>>>> + .num_parents = 1,
>>>> + /*
>>>> + * Display directly handle hdmi pll registers ATM, we need
>>>> + * NOCACHE to keep our view of the clock as accurate as
>>>> + * possible
>>>> + */
>>>
>>> Is it really ?
>>>
>>> Given that HDMI support for the s4 is there yet, the
>>> addresses have changes and the region is no longer a syscon, it is time
>>> for the HDMI driver to get fixed.
> The HDMI PLL is configured in the Uboot phase and does not change the
> frequency in the kernel phase. So we use the NOCACHE flag and
> "ro_ops".
That's no reason to put NOCACHE or ro-ops
If you want the frequencies to be statically assinged, the correct way
would be through assigned-rate in DT I guess.
