On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote: > On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the > ordinal corners of the chip, which our documentation refers to as > "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are > highly configurable & many of the input clocks are optional. > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.example.dtb: clock-controller@38100000: 'clock-output-names' is a required property From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
