Hey all,
PolarFire SoC has 4 clock source blocks, each with 2 PLLs and 2 DLLs,
in the corners of the FPGA fabric. Add bindings, a driver supporting
the PLLs and the requisite changes to the devicetrees for PolarFire
SoC based boards. These clocks were already in use, but which clock
specifically was chosen was decided by the synthesis tool. In our
end-of-September release of our FPGA reference design, constraints will
be added to force the synthesis tool to pick the "north west" CCC,
making it possible to read the configuration from the CCC's registers.
I am mainly looking for feedback on the dt-bindings on this version,
so that if something dt-abi related needs to change it can be done in
advance.
There are no maintainers changes in this series, but they are required
due to the binding rename. I am waiting for some changes queued in the
soc tree before rebasing on a later -rc before including that patch.
Thanks,
Conor.
Changes since v1:
- Stopped using the dt node name to generate the clk name. Rather than
use clock-output-names etc, I just opted to call each PLL after it's
individual base address:
cccrefclk
ccc@38100000_pll0
ccc@38100000_pll0_out3
ccc@38100000_pll0_out2
ccc@38100000_pll0_out1
ccc@38100000_pll0_out0
- dt nodes are now all called "clock-controller"
Conor Dooley (6):
dt-bindings: clk: rename mpfs-clkcfg binding
dt-bindings: clk: document PolarFire SoC fabric clocks
dt-bindings: clk: add PolarFire SoC fabric clock ids
clk: microchip: add PolarFire SoC fabric clock support
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: add the mpfs' fabric clock control
.../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++
...p,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +-
.../devicetree/bindings/riscv/microchip.yaml | 1 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +-
.../boot/dts/microchip/mpfs-icicle-kit.dts | 4 +
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 +
arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +-
drivers/clk/microchip/Makefile | 1 +
drivers/clk/microchip/clk-mpfs-ccc.c | 293 ++++++++++++++++++
.../dt-bindings/clock/microchip,mpfs-clock.h | 23 ++
10 files changed, 458 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%)
create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c
base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
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2.36.1
