On 22/08/2022 12:29, Conor Dooley wrote:
> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> ordinal corners of the chip, which our documentation refers to as
> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> highly configurable & many of the input clocks are optional.
>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> + clock-names:
> + minItems: 2
> + items:
> + - const: pll0_ref0
> + - const: pll0_ref1
> + - const: pll1_ref0
> + - const: pll1_ref1
> + - const: dll0_ref
> + - const: dll1_ref
> +
> + '#clock-cells':
> + const: 1
> + description: |
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell.
> + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
> + PolarFire clock IDs.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - clock-output-names
Meh, didn't notice I had left this here.. Must've crept back in while
I was rebasing my v2 changes.
Either way Kryzysztof, I settled on removing the ordinal based naming
entirely. I could not get trying the ordinal names & then falling back
cleanly enough for my liking, so I dropped the whole thing.
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@38100000 {
> + compatible = "microchip,mpfs-ccc";
> + reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
> + <0x39010000 0x1000>, <0x39020000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
> + <&refclk_ccc>, <&refclk_ccc>;
> + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
> + "dll0_ref", "dll1_ref";
> + };
