From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
On Wed, 10 Aug 2022 09:59:15 +0100, Conor Dooley wrote:
> The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
> of the FPGA IP core. The original binding had no fallback etc, so this
> device tree is valid as is. There was also no functional driver for the
> QSPI IP, so no device with a devicetree from a previous mainline
> release will regress.
>
>
> [...]
Applied to dt-for-next, thanks!
[1/1] riscv: dts: microchip: add qspi compatible fallback
https://git.kernel.org/conor/c/7eac0081a8e9
Thanks,
Conor.
