The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 of the FPGA IP core. The original binding had no fallback etc, so this device tree is valid as is. There was also no functional driver for the QSPI IP, so no device with a devicetree from a previous mainline release will regress. Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@xxxxxxxxxx/ Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- See the link for binding discussion. I'll apply this at some point once the driver makes it upstream. CC: nagasuresh.relli@xxxxxxxxxxxxx CC: valentina.fernandezalanis@xxxxxxxxxxxxx CC: broonie@xxxxxxxxxx CC: devicetree@xxxxxxxxxxxxxxx CC: krzysztof.kozlowski+dt@xxxxxxxxxx CC: robh+dt@xxxxxxxxxx CC: linux-kernel@xxxxxxxxxxxxxxx CC: linux-spi@xxxxxxxxxxxxxxx CC: linux-riscv@xxxxxxxxxxxxxxxxxxx --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 499c2e63ad35..45e3cc659882 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -330,7 +330,7 @@ spi1: spi@20109000 { }; qspi: spi@21000000 { - compatible = "microchip,mpfs-qspi"; + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21000000 0x0 0x1000>; -- 2.36.1
