Microchip's PolarFire SoC QSPI IP core is based on coreQSPI,
so add coreqspi as a fallback to mpfs-qspi.
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@xxxxxxxxxxxxx>
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
.../devicetree/bindings/spi/microchip,mpfs-spi.yaml | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index a47d4923b51b..1051690e3753 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -18,10 +18,12 @@ allOf:
properties:
compatible:
- enum:
- - microchip,mpfs-spi
- - microchip,mpfs-qspi
- - microchip,coreqspi-rtl-v2 # FPGA QSPI
+ oneOf:
+ - items:
+ - const: microchip,mpfs-qspi
+ - const: microchip,coreqspi-rtl-v2
+ - const: microchip,coreqspi-rtl-v2 #FPGA QSPI
+ - const: microchip,mpfs-spi
reg:
maxItems: 1
--
2.25.1
