Hi Krzysztof,
Thank you for your reply.
On 2022/8/5 17:16, Krzysztof Kozlowski wrote:
[ EXTERNAL EMAIL ]
On 05/08/2022 10:57, Yu Tu wrote:
Added information about the S4 SOC PLL Clock controller in DT.
Signed-off-by: Yu Tu <yu.tu@xxxxxxxxxxx>
---
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ff213618a598..a816b1f7694b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -92,6 +92,14 @@ apb4: apb4@fe000000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+ clkc_pll: pll-clock-controller@8000 {
Node names should be generic - clock-controller.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
I will change to clkc_pll: clock-controller@8000, in next version.
Best regards,
Krzysztof
.
