On 10/1/14, 11:31 AM, tthayer@xxxxxxxxxxxxxxxxxxxxx wrote:
> From: Thor Thayer <tthayer@xxxxxxxxxxxxxxxxxxxxx>
>
> Adding the device tree entries needed to support the Altera L2
> cache and OCRAM EDAC.
>
> Signed-off-by: Thor Thayer <tthayer@xxxxxxxxxxxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/socfpga.dtsi | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 4d77ad6..f186957 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -608,7 +608,7 @@
> };
>
> L2: l2-cache@fffef000 {
> - compatible = "arm,pl310-cache";
> + compatible = "arm,pl310-cache", "syscon";
> reg = <0xfffef000 0x1000>;
> interrupts = <0 38 0x04>;
> cache-unified;
> @@ -628,6 +628,24 @@
> clock-names = "biu", "ciu";
> };
>
> + ocram: sram@ffff0000 {
> + compatible = "mmio-sram";
> + reg = <0xffff0000 0x10000>;
> + };
> +
I sent a patch to add the OCRAM node:
http://www.spinics.net/lists/devicetree/msg51117.html
> + l2edac@xffd08140 {
Remove the 'x'.
> + compatible = "altr,l2-edac";
> + reg = <0xffd08140 0x4>;
> + interrupts = <0 36 1>, <0 37 1>;
> + };
> +
> + ocramedac@ffd08144 {
> + compatible = "altr,ocram-edac";
> + reg = <0xffd08144 0x4>;
> + iram = <&ocram>;
> + interrupts = <0 178 1>, <0 179 1>;
> + };
> +
> /* Local timer */
> timer@fffec600 {
> compatible = "arm,cortex-a9-twd-timer";
>
The documentation for these bindings should be included with this patch.
Dinh
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