On 7/12/22 5:14 AM, Samuel Holland wrote: > Hi Linus, > > On 7/11/22 3:58 AM, Linus Walleij wrote: >> On Sun, Jun 26, 2022 at 4:11 AM Samuel Holland <samuel@xxxxxxxxxxxx> wrote: >> >>> D1 contains a pin controller similar to previous SoCs, but with some >>> register layout changes. It includes 6 interrupt-capable pin banks. >>> >>> D1s is a low pin count version of the D1 SoC, with some pins omitted. >>> The remaining pins have the same function assignments as D1. >>> >>> Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> >> >> All 6 patches applied to the pinctrl tree, the last patch 6/6 >> required some fuzzing so please check the result! I do not see anything in patch 6 that would have required a 3-way merge, so I don't understand what the issue was here. > Somehow the version of patch 6 applied to the pinctrl tree did not include the > new driver source file. It only applied changes to existing files (including the > Makefile reference to the new file). > > I also needed to make some minor changes to patch 6 to resolve comments from Andre. > > Is it okay if I send a v2 of just patch 6? Or do I need to send a follow-up > based on what was already applied? I sent a v2 of the whole series: https://lore.kernel.org/linux-gpio/20220713025233.27248-1-samuel@xxxxxxxxxxxx/ Please let me know if you want something different. Regards, Samuel
