On Fri, Jun 03, 2022 at 12:35:57PM +0200, Linus Walleij wrote: > On Fri, Jun 3, 2022 at 11:06 AM Piyush Malgujar <pmalgujar@xxxxxxxxxxx> wrote: > > > The purpose of this pin-cfg entry is different than the standard GPIO pin config usage. > > It is to write a value to GPIO_BIT_CFG register which is used to configure fields like > > pin function, selecting which signal is reported to GPIO output or which signal GPIO > > input need to connect, filters, XOR and output mode. > > Then implement pin control for this driver instead of inventing a custom hack? > https://docs.kernel.org/driver-api/pin-control.html > > Several drivers implement pin control with a GPIO front-end, for example: > drivers/gpio/gpio-pl061.c is used as a front end with > drivers/pinctrl/pinctrl-single.c > > There are also composite drivers in drivers/pinctrl that implement both > pincontrol (incl muxing) and GPIO, such as drivers/pinctrl/pinctrl-sx150x.c > > Yours, > Linus Walleij Hi Linus, Thanks for the reply. But as in this case, we expect a 32 bit reg value via DTS for this driver only from user with internal understanding of marvell soc and this reg bit value can have many different combinations as the register fields can vary for different marvell SoCs. This patch just reads the reg value from DTS and writes it to the register. Thanks, Piyush
