[PATCH 1/4] dt-bindings: phy: samsung,ufs-phy: make pmu-syscon as phandle-array

[Chanho Park <chanho61.park@xxxxxxxxxxx>]

To support secondary ufs phy devices, we need to get an offset value
from pmu-syscon.

Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
---
 .../devicetree/bindings/phy/samsung,ufs-phy.yaml    | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..80c3ec14375a 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -40,9 +40,14 @@ properties:
       - const: tx0_symbol_clk
 
   samsung,pmu-syscon:
-    $ref: '/schemas/types.yaml#/definitions/phandle'
-    description: phandle for PMU system controller interface, used to
-                 control pmu registers bits for ufs m-phy
+    $ref: '/schemas/types.yaml#/definitions/phandle-array'
+    items:
+      - items:
+        - description: phandle for PMU system controller interface, used to
+                       control pmu registers bits for ufs m-phy
+        - description: offset of pmu control register for ufs m-phy
+    description:
+      can be phandle/offset pair. The offset can be optional.
 
 required:
   - "#phy-cells"
@@ -63,7 +68,7 @@ examples:
         compatible = "samsung,exynos7-ufs-phy";
         reg = <0x15571800 0x240>;
         reg-names = "phy-pma";
-        samsung,pmu-syscon = <&pmu_system_controller>;
+        samsung,pmu-syscon = <&pmu_system_controller 0x720>;
         #phy-cells = <0>;
         clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
                  <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
-- 
2.36.1