On Wed, May 04, 2022 at 12:46:37AM +0300, Serge Semin wrote: > Currently almost each platform driver uses its own resets and clocks > naming in order to get the corresponding descriptors. It makes the code > harder to maintain and comprehend especially seeing the DWC PCIe core main > resets and clocks signals set hasn't changed much for about at least one > major IP-core release. So in order to organize things around these signals > we suggest to create a generic interface for them in accordance with the > naming introduced in the DWC PCIe IP-core reference manual: > > Clocks: > - DBI - data bus interface clock (on some DWC PCIe platforms it's > referred as "pclk", "pcie", "sys", "ahb", "cfg", "iface", "gio", "reg", > "pcie_apb_sys"); > - MSTR - AXI-bus master interface clock (some DWC PCIe glue drivers refer > to this clock as "port", "bus", "pcie_bus", > "bus_master/master_bus/axi_m", "pcie_aclk"); > - SLV - AXI-bus slave interface clock (also called as "port", "bus", > "pcie_bus", "bus_slave/slave_bus/axi_s", "pcie_aclk", > "pcie_inbound_axi"); > - PIPE - Core-PCS PIPE interface clock coming from external PHY (it's > normally named by the platform drivers as just "pipe") > - CORE - primary clock of the controller (none of the platform drivers > declare such a clock but in accordance with the ref. manual the devices > may have it separately specified); > - AUX - Auxiliary PMC domain clock (it is named by some platforms as > "pcie_aux" and just "aux") > - REF - Generic reference clock (it is a generic clock source, which can > be used as a signal source for multiple interfaces, some platforms call > it as "ref", "general", "pcie_phy", "pcie_phy_ref"). > > Application resets: > - DBI - Data-bus interface reset (it's CSR interface clock and is normally > called as "apb" though technically it's not APB but DWC PCIe-specific > interface); > apb, sys, > - MSTR -AXI-bus master reset (some platforms call it as "port", "apps", > "bus", "axi_m"); > - SLV - ABI-bus slave reset (some platforms call it as "port", "apps", > "bus", "axi_s"). > > Core resets: > - NON_STICKY - Non-sticky CSR flags reset; > - STICKY - sticky CSR flags reset; > - PIPE - PIPE-interface (Core-PCS) logic reset (some platforms call it > just "pipe"); > - CORE - controller primary reset (resets everything except PMC module, > some platforms refer to this signal as "soft", "pci"); > - PHY - PCS/PHY block reset (strictly speaking it is normally connected to > the out of the external block, but the reference manual says it must be > available for the PMC working correctly, some existing platforms call it > as "pciephy", "phy", "link"); > - HOT - PMC hot reset signal (also called as sleep"); > - PWR - cold reset signal (can be referred as "pwr", "turnoff"). > > As you can see each platform uses it's own naming for basically the same > set of the signals. In the framework of this commit we suggest to add a > set of the clocks and signals identifiers and corresponding names for each > denoted entity. The platforms will be able to use them to define local > mapping tables between the generic identifiers and the available set of > the clocks and resets. The tables can be then utilized to create the > corresponding bulk-arrays, which in its turn can be passed to the > clock/reset-bulk API methods to easily get/enable/disable/put, > get/reset/assert/deassert/put all the handlers at once or, if it's > required, manipulate with the handlers individually. No doubt there is way to much variation here (ummm, Qcom!). Some standardization of names in (new) bindings would be good. That's where we should be defining names IMO. On the driver side, I'd like to see the DW core handle clocks/resets/phys at least for the easy cases of just turn on/off all the clocks and toggle all resets. Perhaps even more minimally, move the clk/reset struct pointers to the DWC core. IOW, I'm not sure this patch is really helpful without some of the above happening. Rob
