On 10/05/2022 14:37, Andrew Lunn wrote: > On Tue, May 10, 2022 at 09:08:08AM +0200, Krzysztof Kozlowski wrote: >> On 10/05/2022 06:14, Chris Packham wrote: >>> >>> Based on the information I have (which isn't much) there is a ref_clk >>> input that is connected to a 25MHz oscillator and then I'm assuming >>> these are all generated from that with various dividers. 25MHz is the >>> only documented option. >>> >>> There doesn't appear to be any documented register where I can read out >>> the divider ratios. It might be nice I could have the fixed osc node and >>> have these 3 clocks derived with fixed divisors but I don't see any what >>> of achieving that. >> >> >> OK, but where are the dividers? The ref_clk is outside of SoC, so should >> be defined in board DTS (at least its rate). If the rest is in the SoC, >> they are usually part of clock controller, because usually they belong >> to some power domain or have some clock gating. > > 25MHz is a 'magic value' in Ethernet, nearly everything is based > around it. And remember this SoC is basically an Ethernet switch with > a small CPU glued on one side. If you gated clocks derived from the > 25MHz reference clock, probably part of your Ethernet switch stops > working, which is the whole point of this SoC. So i doubt there are > gates on the derived clocks. If there is any gating and power domains, > it is generally at a different level. You can power down individual > ports of the Ethernet switch. But generally, there is one bit in a > register somewhere to do that, and you don't have direct control over > clocks and regulators etc. The 25 MHz input clock I understand, it was about other clocks, like spi, axi and core. These clearly look like part of SoC, so defining them with a "stubs" (uncontrollable fixed-clock) is not the best way of modelling an SoC. Although maybe this SoC does not have a proper clock controller and even SPI and AXI clocks are always on? Best regards, Krzysztof
