On 10/05/2022 06:14, Chris Packham wrote: > > Based on the information I have (which isn't much) there is a ref_clk > input that is connected to a 25MHz oscillator and then I'm assuming > these are all generated from that with various dividers. 25MHz is the > only documented option. > > There doesn't appear to be any documented register where I can read out > the divider ratios. It might be nice I could have the fixed osc node and > have these 3 clocks derived with fixed divisors but I don't see any what > of achieving that. OK, but where are the dividers? The ref_clk is outside of SoC, so should be defined in board DTS (at least its rate). If the rest is in the SoC, they are usually part of clock controller, because usually they belong to some power domain or have some clock gating. Best regards, Krzysztof
