>The AXP805 datasheet has this information in the description for REG 1A. >DVM is disabled by default, and when it is enabled, the default ramp rate >is 10mV/15.625 us == 640 uV/us. > >Did you notice any instability without this delay? Actually I write this based on the commit https://github.com/torvalds/linux/commit/ebae33c ("arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3") and https://github.com/ torvalds/linux/commit/fe79ea5 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64"), so I think it's necessary to add this delay. >> @@ -216,6 +222,7 @@ reg_dcdcc: dcdcc { >> regulator-enable-ramp-delay = <32000>; >> regulator-min-microvolt = <810000>; >> regulator-max-microvolt = <1080000>; >> + regulator-ramp-delay = <2500>; > >This change is not related to CPU frequency scaling, so it belongs in a separate >patch (if it is needed). The two commits mentioned above also add this delay to dcdcc regulator. If there is a need for a separate patch, I will send these separately. Thanks, Chukun
