Hi Chukun, On 5/8/22 8:29 AM, Chukun Pan wrote: >> The AXP805 datasheet has this information in the description for REG 1A. >> DVM is disabled by default, and when it is enabled, the default ramp rate >> is 10mV/15.625 us == 640 uV/us. >> >> Did you notice any instability without this delay? > > Actually I write this based on the commit https://github.com/torvalds/linux/commit/ebae33c > ("arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3") and https://github.com/ > torvalds/linux/commit/fe79ea5 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Pine > H64"), so I think it's necessary to add this delay. Thanks for the context! I think the suggestion comes originally from here: https://lore.kernel.org/lkml/20200405115138.vrrvv7spnv6ifm6x@xxxxxxxxxxxx/ >From my reading of that thread, there appear to have been no reliability issues before adding this change. It was just based on the available information at the time. On the other hand, adding this property will cause the CPU to spin for up to 112us in _regulator_do_set_voltage() during each CPU frequency change. So this adds a lot of latency, which I would like to avoid if possible. Regards, Samuel >>> @@ -216,6 +222,7 @@ reg_dcdcc: dcdcc { >>> regulator-enable-ramp-delay = <32000>; >>> regulator-min-microvolt = <810000>; >>> regulator-max-microvolt = <1080000>; >>> + regulator-ramp-delay = <2500>; >> >> This change is not related to CPU frequency scaling, so it belongs in a separate >> patch (if it is needed). > > The two commits mentioned above also add this delay to dcdcc regulator. > If there is a need for a separate patch, I will send these separately. > > Thanks, > Chukun > >
