Hello, On Fri, 2022-04-29 at 13:44 -0500, Nate Drude wrote: > Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), > causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at > the GP_CLK pin. > > Signed-off-by: Nate Drude <nate.d@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/net/adi,adin.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml > index 1129f2b58e98..5fdbbd5aff82 100644 > --- a/Documentation/devicetree/bindings/net/adi,adin.yaml > +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml > @@ -36,6 +36,11 @@ properties: > enum: [ 4, 8, 12, 16, 20, 24 ] > default: 8 > > + adi,clk_rcvr_125_en: > + description: | > + Set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz > + PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin. > + > unevaluatedProperties: false > > examples: The recipients list does not contain a few required ones, adding for awareness Rob, Krzysztof and the devicetree ML. If a new version should be required, please include them. Thanks! Paolo
