On Tue, Apr 19, 2022 at 6:33 PM Atish Patra <atishp@xxxxxxxxxxxx> wrote:
>
> There are no ISA extension defined as 's' & 'u' in RISC-V specifications.
> The misa register defines 's' & 'u' bit as Supervisor/User privilege mode
> enabled. But it should not appear in the ISA extension in the device tree.
>
> Remove those from the allowed ISA extension for kvm.
>
> Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
> ---
> arch/riscv/kvm/vcpu.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 6785aef4cbd4..2e25a7b83a1b 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -43,9 +43,7 @@ const struct kvm_stats_header kvm_vcpu_stats_header = {
> riscv_isa_extension_mask(d) | \
> riscv_isa_extension_mask(f) | \
> riscv_isa_extension_mask(i) | \
> - riscv_isa_extension_mask(m) | \
> - riscv_isa_extension_mask(s) | \
> - riscv_isa_extension_mask(u))
> + riscv_isa_extension_mask(m))
>
> static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
> {
> --
> 2.25.1
>
Sorry. Forgot to add the fixes tag.
Fixes: a33c72faf2d7 (RISC-V: KVM: Implement VCPU create, init and
destroy functions)
--
Regards,
Atish
