On Sun, Apr 17, 2022 at 6:23 PM Dmitry Osipenko
<dmitry.osipenko@xxxxxxxxxxxxx> wrote:
>
> On 4/16/22 13:17, Peter Geis wrote:
> > On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
> > <dmitry.osipenko@xxxxxxxxxxxxx> wrote:
> >>
> >> Hi Peter,
> >>
> >> On 4/16/22 13:05, Peter Geis wrote:
> >>> + pcie2x1: pcie@fe260000 {
> >>> + compatible = "rockchip,rk3568-pcie";
> >>> + #address-cells = <3>;
> >>> + #size-cells = <2>;
> >>> + bus-range = <0x0 0xf>;
> >>> + assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> >>> + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> >>> + <&cru CLK_PCIE20_AUX_NDFT>;
> >>
> >> Why these assigned-clocks are needed? I don't see anything assigned in
> >> this patchset.
> >
> > Ah, those are remnants of early bringup when performance wasn't good
> > and I was manually setting clock rates.
>
> If it's not needed, should it be removed then? Otherwise it looks like
> something is missing in the DT in regards to the assigned clocks.
Yes, it has been removed from the V7.
Thanks!
