Hi Peter,
On 4/16/22 13:05, Peter Geis wrote:
> + pcie2x1: pcie@fe260000 {
> + compatible = "rockchip,rk3568-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xf>;
> + assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> + <&cru CLK_PCIE20_AUX_NDFT>;
Why these assigned-clocks are needed? I don't see anything assigned in
this patchset.
