Add documentation to describe Nuvoton MA35D1 clock driver bindings. Signed-off-by: Jacky Huang <ychuang3@xxxxxxxxxxx> --- .../bindings/clock/nuvoton,ma35d1-clk.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..d0d37c5e84af --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Control Module Binding + +maintainers: + - Chi-Fang Li <cfli0@xxxxxxxxxxx> + - Jacky Huang <ychuang3@xxxxxxxxxxx> + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + const: nuvoton,ma35d1-clk + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + assigned-clocks: + minItems: 5 + maxItems: 5 + + assigned-clock-rates: + minItems: 5 + maxItems: 5 + + nuvoton,clk-pll-mode: + A list of PLL operation mode corresponding to DDRPLL, APLL, EPLL, + and VPLL in sequential. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + items: + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x0 0x40460200 0x0 0x100>; + #clock-cells = <1>; + }; +... -- 2.17.1
