> -----Original Message----- > From: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Sent: 2022年4月15日 5:03 > To: Hongxing Zhu <hongxing.zhu@xxxxxxx>; p.zabel@xxxxxxxxxxxxxx; > bhelgaas@xxxxxxxxxx; lorenzo.pieralisi@xxxxxxx; robh@xxxxxxxxxx; > shawnguo@xxxxxxxxxx; vkoul@xxxxxxxxxx; alexander.stein@xxxxxxxxxxxxxxx > Cc: linux-phy@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; > linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; > linux-kernel@xxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; dl-linux-imx > <linux-imx@xxxxxxx> > Subject: Re: [PATCH v2 5/7] arm64: dts: imx8mp: add the iMX8MP PCIe > support > > Am Montag, dem 07.03.2022 um 17:07 +0800 schrieb Richard Zhu: > > Add the i.MX8MP PCIe support. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> > > --- > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 > > ++++++++++++++++++++++- > > 1 file changed, 45 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > index b40a5646f205..e7b3d8029e34 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -5,6 +5,7 @@ > > > > #include <dt-bindings/clock/imx8mp-clock.h> > > #include <dt-bindings/power/imx8mp-power.h> > > +#include <dt-bindings/reset/imx8mp-reset.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/input/input.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > @@ -375,7 +376,8 @@ iomuxc: pinctrl@30330000 { > > }; > > > > gpr: iomuxc-gpr@30340000 { > > - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; > > + compatible = "fsl,imx8mp-iomuxc-gpr", > > + "fsl,imx6q-iomuxc-gpr", "syscon"; > > reg = <0x30340000 0x10000>; > > }; > > > > @@ -965,6 +967,17 @@ aips4: bus@32c00000 { > > #size-cells = <1>; > > ranges; > > > > + pcie_phy: pcie-phy@32f00000 { > > + compatible = "fsl,imx8mp-pcie-phy"; > > + reg = <0x32f00000 0x10000>; > > + resets = <&src IMX8MP_RESET_PCIEPHY>, > > + <&src IMX8MP_RESET_PCIEPHY_PERST>; > > + reset-names = "pciephy", "perst"; > > + power-domains = <&hsio_blk_ctrl > IMX8MP_HSIOBLK_PD_PCIE_PHY>; > > + #phy-cells = <0>; > > + status = "disabled"; > > + }; > > + > > hsio_blk_ctrl: blk-ctrl@32f10000 { > > compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; > > reg = <0x32f10000 0x24>; > > @@ -980,6 +993,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { > > }; > > }; > > > > + pcie: pcie@33800000 { > > + compatible = "fsl,imx8mp-pcie"; > > + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; > > + reg-names = "dbi", "config"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + bus-range = <0x00 0xff>; > > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 > 0x00010000 /* downstream I/O 64KB */ > > + 0x82000000 0 0x18000000 0x18000000 0 > 0x07f00000>; /* non-prefetchable memory */ > > + num-lanes = <1>; > > + num-viewport = <4>; > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "msi"; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > > + fsl,max-link-speed = <3>; > > I believe that imx6_pcie_start_link does not properly handle Gen3 speeds. Good caught. The according link_gen condition should be changed in driver too. Would be changed in next version. Thanks. Best Regards Richard Zhu > > Regards, > Lucas > > > + linux,pci-domain = <0>; > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; > > + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; > > + reset-names = "apps", "turnoff"; > > + phys = <&pcie_phy>; > > + phy-names = "pcie-phy"; > > + status = "disabled"; > > + }; > > + > > gpu3d: gpu@38000000 { > > compatible = "vivante,gc"; > > reg = <0x38000000 0x8000>; >