> -----Original Message-----
> From: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Sent: 2022年4月15日 5:05
> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>; p.zabel@xxxxxxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; lorenzo.pieralisi@xxxxxxx; robh@xxxxxxxxxx;
> shawnguo@xxxxxxxxxx; vkoul@xxxxxxxxxx; alexander.stein@xxxxxxxxxxxxxxx
> Cc: linux-phy@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; dl-linux-imx
> <linux-imx@xxxxxxx>
> Subject: Re: [PATCH v2 6/7] arm64: dts: imx8mp-evk: Add PCIe support
>
> Am Montag, dem 07.03.2022 um 17:07 +0800 schrieb Richard Zhu:
> > Add PCIe support on i.MX8MP EVK board.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55
> > ++++++++++++++++++++
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index 2eb943210678..ed77455a3f73 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -5,6 +5,7 @@
> >
> > /dts-v1/;
> >
> > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> > #include "imx8mp.dtsi"
> >
> > / {
> > @@ -33,6 +34,12 @@ memory@40000000 {
> > <0x1 0x00000000 0 0xc0000000>;
> > };
> >
> > + pcie0_refclk: pcie0-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > reg_can1_stby: regulator-can1-stby {
> > compatible = "regulator-fixed";
> > regulator-name = "can1-stby";
> > @@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
> > enable-active-high;
> > };
> >
> > + reg_pcie0: regulator-pcie {
> > + compatible = "regulator-fixed";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie0_reg>;
> > + regulator-name = "MPCIE_3V3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +
> > reg_usdhc2_vmmc: regulator-usdhc2 {
> > compatible = "regulator-fixed";
> > pinctrl-names = "default";
> > @@ -297,6 +315,30 @@ pca6416: gpio@20 {
> > };
> > };
> >
> > +&pcie_phy {
> > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > + clocks = <&pcie0_refclk>;
> > + clock-names = "ref";
> > + status = "okay";
> > +};
> > +
> > +&pcie{
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie0>;
> > + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > + <&clk IMX8MP_CLK_PCIE_ROOT>,
> > + <&clk IMX8MP_CLK_HSIO_AXI>;
> > + clock-names = "pcie", "pcie_aux", "pcie_bus";
> > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> > + <&clk IMX8MP_CLK_PCIE_AUX>;
> > + assigned-clock-rates = <500000000>, <10000000>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
>
> You don't need to set the IMX8MP_CLK_HSIO_AXI clock rate here, that's
> already don't by the power-domain, as it is keeping this bus clock active. Only
> need to set the PCIE_AUX rate here.
Thanks, for your review comments.
Would be changed in next version.
Best Regards
Richard Zhu
>
> Regards,
> Lucas
>
> > + <&clk IMX8MP_SYS_PLL2_50M>;
> > + vpcie-supply = <®_pcie0>;
> > + status = "okay";
> > +};
> > +
> > &snvs_pwrkey {
> > status = "okay";
> > };
> > @@ -442,6 +484,19 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA
> 0x400001c3
> > >;
> > };
> >
> > + pinctrl_pcie0: pcie0grp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open
> drain, pull up */
> > + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
> > + >;
> > + };
> > +
> > + pinctrl_pcie0_reg: pcie0reggrp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
> > + >;
> > + };
> > +
> > pinctrl_pmic: pmicgrp {
> > fsl,pins = <
> > MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
>
