On Sat, 09 Apr 2022 03:38:55 +0100,
Brad Larson <brad@xxxxxxxxxxx> wrote:
>
> On Thu, Apr 7, 2022 at 12:57 AM Marc Zyngier <maz@xxxxxxxxxx> wrote:
> >
> > > + gic: interrupt-controller@800000 {
> > > + compatible = "arm,gic-v3";
> > > + #interrupt-cells = <3>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > + interrupt-controller;
> > > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */
> > > + <0x0 0xa00000 0x0 0x200000>; /* GICR */
> >
> > You are still missing the GICV and GICH regions that are
> > provided by the CPU. I already pointed that out in [1].
> >
> > The Cortex-A72 TRM will tell you where to find them (at
> > an offset from PERIPHBASE).
>
> Hi Marc,
>
> Got the addresses, neither region is used, and will be included in the
> next submission.
Not sure what you mean by these regions being unused here (the Linux
kernel definitely makes use of them). Note that you'll also need to
add GICC (which I forgot to mention above).
M.
--
Without deviation from the norm, progress is not possible.
