Hi Andrew, On 7/04/22 00:36, Andrew Lunn wrote: > On Wed, Apr 06, 2022 at 03:21:56PM +1200, Chris Packham wrote: >> This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips >> from Marvell. It is based on the Marvell SDK with additions for various >> (non-gpio) pin configurations based on the datasheet. >> >> Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx> >> Reviewed-by: Andrew Lunn <andrew@xxxxxxx> >> --- >> >> Notes: >> Changes in v3: >> - Use mmio instead of syscon > Hi Chris > > syscon is used when the register space is shared with other > devices. Is that not the case here? You can share mmio spaces, but you > have to use the correct call to reserve it, so that the system knows > it is to be shared. Or are all the pinctl registers contiguous and you > are only reserve just the registers you need, leaving other drivers > fee to take what they need? > > I'm just trying to ensure you are not going to have trouble later when > you add other drivers. The pinctrl registers that are used are all continguous (0x80020100 -- 0x8002011c) . There is a block called the "CnM RFU" which is near the pinctrl registers (but a different section in the datasheet) which has some peripheral controls. There is also some odd registers (eMMC PHY and RFU interrupts) in the MPP section of the document but outside the range that this driver uses. I can't tell if this is similar to the RFU block on the discrete Armada 64 SoCs, the integrated SoC/Switch chips tend to be a bit of a frankenstiens monster of IP blocks. I really wish I could just share the datasheet but you know how hardware vendors like their NDAs. > > Andrew
