On Tue, Jan 25, 2022 at 12:45:53PM -0800, Stephen Boyd wrote:
> Quoting Ansuel Smith (2022-01-21 13:03:35)
> > Add additional freq supported for the sdc table.
> >
> > Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
> > ---
> > drivers/clk/qcom/gcc-ipq806x.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> > index 77bc3d94f580..dbd61e4844b0 100644
> > --- a/drivers/clk/qcom/gcc-ipq806x.c
> > +++ b/drivers/clk/qcom/gcc-ipq806x.c
> > @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
> > { 20210000, P_PLL8, 1, 1, 19 },
> > { 24000000, P_PLL8, 4, 1, 4 },
> > { 48000000, P_PLL8, 4, 1, 2 },
> > + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */
>
> Why the comment and fake rate? Can it be 51200000 instead and drop the
> comment?
I will add the related reason in the commit.
We cannot achieve exact 52Mhz(jitter free) clock using PLL8.
As per the MND calculator the closest possible jitter free clock
using PLL8 is 51.2Mhz. This patch adds the values, which will provide
jitter free 51.2Mhz when the requested frequency is 52mhz.
--
Ansuel
