2014-08-14 17:11 GMT-07:00 Florian Fainelli <f.fainelli@xxxxxxxxx>:
> Add a very minimalistic BCM63138 Device Tree include file which
> describes the BCM63138 SoC with only the basic set of required
> peripherals:
>
> - Cortex A9 CPUs
> - ARM GIC
> - ARM SCU
> - PL310 Level-2 cache controller
> - ARM TWD & Global timers
> - ARM TWD watchdog
> - legacy MIPS bus (UBUS)
> - BCM6345-style UARTs (disabled by default)
>
> Since the PL310 L2 cache controller does not come out of reset with
> correct default values, we need to override the 'cache-sets' and
> 'cache-size' properties to get its geometry right.
>
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
[snip]
> + /* ARM bus */
> + axi@80000000 {
> + compatible = "simple-bus";
> + ranges = <0 0x80000000 0x84000>;
I made a typo here, the range declared here is narrower than it really
is, I will re-submit this after getting some more feedback. Thanks!
--
Florian
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