On Friday 08 October 2021 15:28:38 Robert Marko wrote:
> > > + cp0_pcie_reset_pins: cp0-pcie-reset-pins {
> > > + marvell,pins = "mpp9";
> > > + marvell,function = "gpio";
> >
> > Now I spotted this. Why is PERST# pin configured into gpio mode? Is
> > there some issue that this pin in pcie mode is not working properly,
> > that PCIe controller cannot handle it correctly? Or something else?
>
> Its because I have seen way too many broken controllers when it comes
> to PERST and
> other Armada 7k/8k devices are using it in GPIO mode as well.
> Just look at the number of conversions back to GPIO for other
> platforms as there is always some bug.
I know that A3720 has broken PERST# control in PCIe block... or at least
I was not able to figure out how A3720 PCIe block can control PERST#. So
configuring it in gpio mode and let PERST# to be controlled manually via
gpio by the software is the workaround.
I just wanted to know if A7k/A8k/CN913x is also broken in the same way
as A3720.
Or it it just a configuration workaround for missing driver or missing
proper software setup.
HW bugs like this should be properly documented and not hidden behind
some configuration in DTS file. And reported to HW vendors.
