Some device set the switch to exchange the mac0 port with mac6 port. Add
support for this in the qca8k driver. Also add support for SGMII rx/tx
clock falling edge. This is only present for pad0, pad5 and pad6 have
these bit reserved from Documentation.
Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
Signed-off-by: Matthew Hagan <mnhagan88@xxxxxxxxx>
---
drivers/net/dsa/qca8k.c | 33 +++++++++++++++++++++++++++++++++
drivers/net/dsa/qca8k.h | 3 +++
2 files changed, 36 insertions(+)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 5bce7ac4dea7..3a040a3ed58e 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -973,6 +973,34 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
return ret;
}
+static int
+qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv)
+{
+ struct device_node *node = priv->dev->of_node;
+ u32 mask = 0;
+ int ret = 0;
+
+ /* Swap MAC0-MAC6 */
+ if (of_property_read_bool(node, "qca,mac6-exchange"))
+ mask |= QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG;
+
+ /* SGMII Clock phase configuration */
+ if (of_property_read_bool(node, "qca,sgmii-rxclk-falling-edge"))
+ mask |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
+
+ if (of_property_read_bool(node, "qca,sgmii-txclk-falling-edge"))
+ mask |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
+
+ if (mask)
+ ret = qca8k_rmw(priv, QCA8K_REG_PORT0_PAD_CTRL,
+ QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG |
+ QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
+ QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
+ mask);
+
+ return ret;
+}
+
static int
qca8k_setup(struct dsa_switch *ds)
{
@@ -1006,6 +1034,11 @@ qca8k_setup(struct dsa_switch *ds)
if (ret)
return ret;
+ /* Configure additional PORT0_PAD_CTRL properties */
+ ret = qca8k_setup_port0_pad_ctrl_reg(priv);
+ if (ret)
+ return ret;
+
/* Enable CPU Port */
ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index fc7db94cc0c9..3fded69a6839 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -35,6 +35,9 @@
#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
#define QCA8K_REG_PORT0_PAD_CTRL 0x004
+#define QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG BIT(31)
+#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
+#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
#define QCA8K_REG_PORT5_PAD_CTRL 0x008
#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
--
2.32.0
