Hi Shubhrajyoti,
My name is Zhengxun and I am the engineer from Macronix. We are
using the platform PicoZed 7015/7030 SOM (System On Module),
which is based on Xilinx Zynq®-7000 All Programmable (AP) SoC to
verify our Flash driver. Of course, we are also using your clock
wizard, our version seems to be v5.2, but something went wrong.
+static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int err;
+ u32 value;
+ unsigned long flags = 0;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ value = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+ /* Cap the value to max */
+ min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE);
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
Why phase always set to zero? We want to support DTR operation in
Flash driver. Can you add a set_phase function to adjust the phase?
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
+ value, value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ goto err_reconfig;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
+ value, value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
According to pg015-clk-wiz.pdf, Clocking Wizard v5.2 and later, need to write
0x00000007 followed by 0x00000002 into Clock Configuration Register 23, to
consolidate the redundant bits that the IP has upgraded, right?
Can you compatible to v5.2?
Thanks,
Zhengxun
