Hi Nava, On Fri, Jan 22, 2021 at 10:34:15AM +0000, Nava kishore Manne wrote: > Hi Moritz, > > Thanks for the review. > Please find my response inline. > > > -----Original Message----- > > From: Moritz Fischer <mdf@xxxxxxxxxx> > > Sent: Tuesday, January 19, 2021 6:03 AM > > To: Nava kishore Manne <navam@xxxxxxxxxx> > > Cc: mdf@xxxxxxxxxx; trix@xxxxxxxxxx; robh+dt@xxxxxxxxxx; Michal Simek > > <michals@xxxxxxxxxx>; linux-fpga@xxxxxxxxxxxxxxx; > > devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > > kernel@xxxxxxxxxxxxxxx; git <git@xxxxxxxxxx>; chinnikishore369@xxxxxxxxx; > > Appana Durga Kedareswara Rao <appanad@xxxxxxxxxx> > > Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver > > > > Hi Nava, > > > > On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne wrote: > > > This patch adds driver for versal fpga manager. > > Nit: Add support for Xilinx Versal FPGA manager > > Will fix in v2. > > > > > > > PDI source type can be DDR, OCM, QSPI flash etc.. > > No idea what PDI is :) > > Programmable device image (PDI). > This file is generated by Xilinx Vivado tool and it contains configuration data objects. > > > > But driver allocates memory always from DDR, Since driver supports > > > only DDR source type. > > > > > > Signed-off-by: Appana Durga Kedareswara rao > > > <appana.durga.rao@xxxxxxxxxx> > > > Signed-off-by: Nava kishore Manne <nava.manne@xxxxxxxxxx> > > > --- > > > drivers/fpga/Kconfig | 8 ++ > > > drivers/fpga/Makefile | 1 + > > > drivers/fpga/versal-fpga.c | 149 > > > +++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 158 insertions(+) > > > create mode 100644 drivers/fpga/versal-fpga.c > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > > 5645226ca3ce..9f779c3a6739 100644 > > > --- a/drivers/fpga/Kconfig > > > +++ b/drivers/fpga/Kconfig > > > @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > > to configure the programmable logic(PL) through PS > > > on ZynqMP SoC. > > > > > > +config FPGA_MGR_VERSAL_FPGA > > > + tristate "Xilinx Versal FPGA" > > > + depends on ARCH_ZYNQMP || COMPILE_TEST > > > + help > > > + Select this option to enable FPGA manager driver support for > > > + Xilinx Versal SOC. This driver uses the versal soc firmware > > > + interface to load programmable logic(PL) images > > > + on versal soc. > > > endif # FPGA > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > > d8e21dfc6778..40c9adb6a644 100644 > > > --- a/drivers/fpga/Makefile > > > +++ b/drivers/fpga/Makefile > > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += > > ts73xx-fpga.o > > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > > obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o > > > obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o > > > > > > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c > > > new file mode 100644 index 000000000000..2a42aa78b182 > > > --- /dev/null > > > +++ b/drivers/fpga/versal-fpga.c > > > @@ -0,0 +1,149 @@ > > > +// SPDX-License-Identifier: GPL-2.0+ > > > +/* > > > + * Copyright (C) 2021 Xilinx, Inc. > > > + */ > > > + > > > +#include <linux/dma-mapping.h> > > > +#include <linux/fpga/fpga-mgr.h> > > > +#include <linux/io.h> > > > +#include <linux/kernel.h> > > > +#include <linux/module.h> > > > +#include <linux/of_address.h> > > > +#include <linux/string.h> > > > +#include <linux/firmware/xlnx-zynqmp.h> > > > + > > > +/* Constant Definitions */ > > > +#define PDI_SOURCE_TYPE 0xF > > > + > > > +/** > > > + * struct versal_fpga_priv - Private data structure > > > + * @dev: Device data structure > > > + * @flags: flags which is used to identify the PL Image type > > > + */ > > > +struct versal_fpga_priv { > > > + struct device *dev; > > > + u32 flags; > > This seems unused ... please introduce them when/if you start using them. > > Will fix in v2. > > > > +}; > > > + > > > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, > > > + struct fpga_image_info *info, > > > + const char *buf, size_t size) { > > > + struct versal_fpga_priv *priv; > > > + > > > + priv = mgr->priv; > > > + priv->flags = info->flags; > > ? What uses this ? It seems this function could just be 'return 0' right now. > > Will fix in v2. > > > > + > > > + return 0; > > > +} > > > + > > > +static int versal_fpga_ops_write(struct fpga_manager *mgr, > > > + const char *buf, size_t size) > > > +{ > > > + struct versal_fpga_priv *priv; > > > + dma_addr_t dma_addr = 0; > > > + char *kbuf; > > > + int ret; > > > + > > > + priv = mgr->priv; > > > + > > > + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, > > GFP_KERNEL); > > > + if (!kbuf) > > > + return -ENOMEM; > > > + > > > + memcpy(kbuf, buf, size); > > > + > > > + wmb(); /* ensure all writes are done before initiate FW call */ > > > + > > > + ret = zynqmp_pm_load_pdi(PDI_SOURCE_TYPE, dma_addr); > > > + > > > + dma_free_coherent(priv->dev, size, kbuf, dma_addr); > > > + > > > + return ret; > > > +} > > > + > > > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, > > > + struct fpga_image_info *info) > > > +{ > > > + return 0; > > > +} > > > + > > > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager > > > +*mgr) { > > > + return FPGA_MGR_STATE_OPERATING; > > Is that always the case? Shouldn't that be FPGA_MGR_STATE_UNKNOWN? > > For Versal SoC base PDI is always configured prior to Linux boot up. So I make the fpga state as OPERATING. > Please let know if it is not a proper implementation will think about the alternate solution. So you're saying I can't boot a Versal SoC without a PDI / Bitstream loaded? Interesting :) > > > > +} > > > + > > > +static const struct fpga_manager_ops versal_fpga_ops = { > > > + .state = versal_fpga_ops_state, > > > + .write_init = versal_fpga_ops_write_init, > > > + .write = versal_fpga_ops_write, > > > + .write_complete = versal_fpga_ops_write_complete, }; > > > + > > > +static int versal_fpga_probe(struct platform_device *pdev) { > > > + struct device *dev = &pdev->dev; > > > + struct versal_fpga_priv *priv; > > > + struct fpga_manager *mgr; > > > + int err, ret; > > Please pick one, err or ret. 'err' seems unused? > > Will fix in v2. > > > > + > > > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > > > + if (!priv) > > > + return -ENOMEM; > > > + > > > + priv->dev = dev; > > > + ret = dma_set_mask_and_coherent(&pdev->dev, > > DMA_BIT_MASK(32)); > > > + if (ret < 0) { > > > + dev_err(dev, "no usable DMA configuration"); > > Nit: "no usable DMA configuration\n" > > Will fix in v2. > > > > + return ret; > > > + } > > > + > > > + mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager", > > > + &versal_fpga_ops, priv); > > > + if (!mgr) > > > + return -ENOMEM; > > > + > > > + platform_set_drvdata(pdev, mgr); > > > + > > > > Replace this part: > > > + err = fpga_mgr_register(mgr); > > > + if (err) { > > > + dev_err(dev, "unable to register FPGA manager"); > > > + fpga_mgr_free(mgr); > > > + return err; > > > + } > > > > with: > > return devm_fpga_mgr_register(mgr); > > > > I tried to get rid of the boilerplate, since every driver repeats it (and above > > calling fpga_mgr_free(mgr) on a devm_fpga_mgr_create() created FPGA > > manager is wrong?) :) > > Thanks for pointing it. Will fix in v2. > > > > + > > > + return 0; > > > +} > > > + > > > > Then > > > +static int versal_fpga_remove(struct platform_device *pdev) { > > > + struct fpga_manager *mgr = platform_get_drvdata(pdev); > > > + > > > + fpga_mgr_unregister(mgr); > > > + fpga_mgr_free(mgr); > > > + > > > + return 0; > > > +} > > drop this since cleanup is now automatic. > > Thanks for pointing it. Will fix in v2. > > > > + > > > +static const struct of_device_id versal_fpga_of_match[] = { > > > + { .compatible = "xlnx,versal-fpga", }, > > > + {}, > > > +}; > > > + > > Nit: Drop the newline > > Will fix in v2. > > > > +MODULE_DEVICE_TABLE(of, versal_fpga_of_match); > > > + > > > +static struct platform_driver versal_fpga_driver = { > > > + .probe = versal_fpga_probe, > > > + .remove = versal_fpga_remove, > > > + .driver = { > > > + .name = "versal_fpga_manager", > > > + .of_match_table = of_match_ptr(versal_fpga_of_match), > > > + }, > > > +}; > > > + > > Nit: Drop the newline > > Will fix in v2. > > Regards, > Navakishore. - Moritz