The Canaan Kendryte K210 RISC-V SoC includes a DesignWare apb_ssi V4 SPI controller implemented with a maximum data frame size of 32-bits (SSI_MAX_XFER_SIZE=32 synthesis parameter). This series of patches adds support for this SoC by implementing support for the 32-bits xfer size configuration. This is done in patch 2. Patch 3 introduces a workaround for a HW bug on this SoC which triggers RX FIFO overrun errors when the RX FIFO fills up to its maximum detected depth of 32. The patch manually reduces the fifo depth to 31. The first patch documents the new compatible string "canaan,k210-spi" used to identify this SoC. Changes from v2: * Moved DT bindings update patch first in the series * Tweaked comments for the DFS32 detection code as suggested by Serge * Added Serge's Acked-by tag to patch 2. Changes from v1: * Fixed patch 1 as suggested by Serge: change capability flag name to DW_SPI_CAP_DFS32 and fixed the capability detection to use the regular position of the dfs filed rather than the new position with DFS32. Also enable DW_SPI_CAP_DFS32 for SPI slaves. * Added Serge's Acked-by tag to patch 2 and 3. Damien Le Moal (3): dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller spi: dw: Add support for 32-bits max xfer size spi: dw: Add support for the Canaan K210 SoC SPI .../bindings/spi/snps,dw-apb-ssi.yaml | 2 + drivers/spi/spi-dw-core.c | 44 ++++++++++++++++--- drivers/spi/spi-dw-mmio.c | 16 +++++++ drivers/spi/spi-dw.h | 5 +++ 4 files changed, 60 insertions(+), 7 deletions(-) -- 2.28.0
