On 25 November 2020 7:44:10 AM IST, Stephen Boyd <sboyd@xxxxxxxxxx> wrote: >Quoting Manivannan Sadhasivam (2020-11-18 23:27:11) >> diff --git >a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml >b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml >> new file mode 100644 >> index 000000000000..9d8981817ae3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml >> @@ -0,0 +1,73 @@ >[...] >> + >> +properties: >> + compatible: >> + const: qcom,gcc-sdx55 >> + >> + clocks: >> + items: >[...] >> + - description: PLL test clock source >> + >> + clock-names: >> + items: >[...] >> + - const: core_bi_pll_test_se > >Is it optional? As far as I know this clk has never been implemented >because it's a hardware validation thing and not used otherwise. It is implemented in drivers but not used as you said. But since it is the parent clk of PLLs I'm not sure we can make it optional. Thanks, Mani -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
