Quoting Manivannan Sadhasivam (2020-11-18 23:27:11) > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > new file mode 100644 > index 000000000000..9d8981817ae3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > @@ -0,0 +1,73 @@ [...] > + > +properties: > + compatible: > + const: qcom,gcc-sdx55 > + > + clocks: > + items: [...] > + - description: PLL test clock source > + > + clock-names: > + items: [...] > + - const: core_bi_pll_test_se Is it optional? As far as I know this clk has never been implemented because it's a hardware validation thing and not used otherwise.
