On Tue, 25 Aug 2020 05:06:19 PDT (-0700), yash.shah@xxxxxxxxxx wrote:
The series add supports for SiFive DDR controller driver. This driver
is use to manage the Cadence DDR controller present in SiFive SoCs.
Currently it manages only the EDAC feature of the DDR controller.
The series also adds Memory controller EDAC support for SiFive platform.
It register for notifier event from SiFive DDR controller driver.
The series is tested and based on Linux v5.8.
For testing on Hifive Unleashed:
1. Enable the ECC bit of DDR controller during DDR initialization
2. Erase the entire DRAM in bootloader stage
3. Using FWC feature of DDR controller force ecc error to test
Yash Shah (3):
dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive
SoCs
soc: sifive: Add SiFive specific Cadence DDR controller driver
edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs
.../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 117 ++++++++++++
drivers/soc/sifive/Kconfig | 6 +
drivers/soc/sifive/Makefile | 3 +-
drivers/soc/sifive/sifive_ddr.c | 207 +++++++++++++++++++++
include/soc/sifive/sifive_ddr.h | 73 ++++++++
7 files changed, 447 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
create mode 100644 drivers/soc/sifive/sifive_ddr.c
create mode 100644 include/soc/sifive/sifive_ddr.h
Thanks. These look good to me and I'm happy to take them through the RISC-V
tree, but I'm going to wait for a bit to see if there are any comments from the
maintainers of the various subsystems before doing so.
