On Wed, 13 May 2020 20:22:37 +0300, Laurent Pinchart wrote: > From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xxxxxxxxxx> > > Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed > Processing System Gigabit Transceiver which provides PHY capabilities to > USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. > > Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xxxxxxxxxx> > Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > --- > Changes since v7: > > - Switch to GPL-2.0-only OR BSD-2-Clause > > Changes since v6: > > - Fixed specification of compatible-dependent xlnx,tx-termination-fix > property > - Dropped status property from example > - Use 4 spaces to indent example > > Changes since v5: > > - Document clocks and clock-names properties > - Document resets and reset-names properties > - Replace subnodes with an additional entry in the PHY cells > - Drop lane frequency PHY cell, replaced by reference clock phandle > - Convert bindings to YAML > - Reword the subject line > - Drop Rob's R-b as the bindings have significantly changed > - Drop resets and reset-names properties > --- > .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++ > include/dt-bindings/phy/phy.h | 1 + > 2 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
