There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R <r.sricharan@xxxxxx> Signed-off-by: Nishanth Menon <nm@xxxxxx> Cc: Benoit Cousson <bcousson@xxxxxxxxxxxx> Cc: Santosh Shilimkar <santosh.shilimkar@xxxxxx> Cc: Rajendra Nayak <rnayak@xxxxxx> Cc: Tony Lindgren <tony@xxxxxxxxxxx> Tested-by: Darren Etheridge <detheridge@xxxxxx> Tested-by: Roger Quadros <rogerq@xxxxxx> --- [V6] Reordered patch 3 from V5 to patch 1 arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 149b550..52df16a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
