On Fri, Nov 01, 2019 at 12:52:00AM +0200, Leonard Crestez wrote: > Add initial dt bindings for the interconnects inside i.MX chips. > Multiple external IPs are involved but SOC integration means the > software controllable interfaces are very similar. > > Single node also acts as interconnect provider if #interconnect-cells is > present. > > Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx> > Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx> > --- > .../devicetree/bindings/devfreq/imx.yaml | 83 +++++++++++++++++++ bindings/interconnect/ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml > > diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml > new file mode 100644 > index 000000000000..bfc825407764 > --- /dev/null > +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/devfreq/imx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Generic i.MX bus frequency device i.MX8 specific? > + > +maintainers: > + - Leonard Crestez <leonard.crestez@xxxxxxx> > + > +description: | > + The i.MX SoC family has multiple buses for which clock frequency (and > + sometimes voltage) can be adjusted. > + > + Some of those buses expose register areas mentioned in the memory maps as GPV > + ("Global Programmers View") but not all. Access to this area might be denied > + for normal (non-secure) world. > + > + The buses are based on externally licensed IPs such as ARM NIC-301 and > + Arteris FlexNOC but DT bindings are specific to the integration of these bus > + interconnect IPs into imx SOCs. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - fsl,imx8mn-nic > + - fsl,imx8mm-nic > + - fsl,imx8mq-nic > + - const: fsl,imx8m-nic > + - items: > + - enum: > + - fsl,imx8mn-noc > + - fsl,imx8mm-noc > + - fsl,imx8mq-noc > + - const: fsl,imx8m-noc > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + operating-points-v2: true > + > + devfreq: > + description: | > + Phandle to another devfreq device to match OPPs with by using the > + passive governor. > + $ref: "/schemas/types.yaml#/definitions/phandle" > + > + '#interconnect-cells': > + description: | > + If specified then also act as an interconnect provider. Should only be > + set once per soc on main noc. > + const: 1 > + > + interconnect-node-id: Looks like common property, but it's not... Generally, we don't do indexes or instance ids. So it needs a better explanation or drop this. The driver side looks like an odd marriage between interconnect and devfreq drivers that needs better integration, but I'm not all that familar with either. > + description: | > + i.MX chips have multiple scalable buses based on the same IP, this is > + used to distinguish between. Uses same identifier namespace as consumer It's not names, so number space? Just guessing because there's no type nor example. > + "interconnects" property, for example one of the values in > + "include/dt-bindings/interconnect/imx8mm.h" > + > + const: 1 > + > +required: > + - compatible > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mm-clock.h> > + noc: noc@32700000 { > + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MM_CLK_NOC>; > + operating-points-v2 = <&noc_opp_table>; > + }; > -- > 2.17.1 >
