On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> usdhc's clock rate is different according to different devices
> connected, so clock rate assignment should be placed in board
> DT according to different devices connected on each usdhc port.
I think it should be fine that we have a reasonable default settings in
soc.dtsi, and boards that need a different setup can overwrite the
settings in board.dts.
Shawn
>
> Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ------
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> index 91eef97..a3f8cf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -133,6 +133,8 @@
> &usdhc1 {
> #address-cells = <1>;
> #size-cells = <0>;
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <4>;
> @@ -149,6 +151,8 @@
>
> /* SD */
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 88dd9132..d3d26cc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -137,6 +137,8 @@
> };
>
> &usdhc1 {
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <8>;
> @@ -147,6 +149,8 @@
> };
>
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 2d69f1a..9646a41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -368,8 +368,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> status = "disabled";
> };
> @@ -383,8 +381,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_1>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> @@ -400,8 +396,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_2>;
> status = "disabled";
> };
> --
> 2.7.4
>
